The phase locked loop (PLL) is one of the basic building blocks in circuits of today's advanced system designs. The charge pump based phase locked loops are utilized in most devices that synthesize a high-frequency reference signal. This means that most modern day communication systems, data encoders/decoders, CPU chips, cell phones, and digital radios have one or more embedded charge pumps.
FIG. 1 depicts a block diagram of a prior art phase locked loop 100 having a current-based charge pump 102. PLL 100 also includes a phase/frequency detector 104, a loop filter 106, a voltage controlled oscillator (VCO) 108, and a divider 110. In operation, the voltage output of the charge pump 102 is supplied to the loop filter 106, e.g., a single capacitor or multiple capacitors possibly with one or more resistors. The loop filter in turn is the control input to the VCO. As a PLL continuously operates, the phase/frequency detector 104 compares the feedback clock signal to a reference clock signal. In response to an error signal (a difference indicated by the comparison), the phase/frequency detector 104 sends an UP or DOWN signal to the charge pump 102, which in turn adjusts the voltage output of the loop filter 106. The loop filter 106 then adjusts the output of the VCO 108, which provides its output to divider 110 to again provide an input to phase/frequency detector 104. The cycle then repeats as needed to achieve a lock on the desired signal, e.g., reference clock signal.
The main contributors to power consumption in prior art PLLs such as 100 are the charge pump 102 and the VCO 108; the phase/frequency detector 104, loop filter 106, and divider(s) 110 generally have smaller power consumption. Prior art PLL charge pumps constantly consume current in the bias circuitry. For example, in a prior art PLL, a current-based charge pump typically consumes on average 0.5 to 1.0 mW of power for a supply voltage of 1.8 V.
FIG. 2 depicts a circuit diagram 200 of the prior art phase locked loop 100 of FIG. 1. Charge pump 102 includes two current mirrors with current sources 202 and 204, respectively. In response to UP or DOWN signals from the phase/frequency detector 104, the current sources 202 and 204 can be isolated from or connected to loop filter 106 by switches 206 and 208, respectively.
Prior art PLL charge pumps, such as shown in FIG. 2, are current-based devices that act like an ideal integrators where the output voltage, CP_Output, is equivalent to the following:
                                          V            c                    ⁡                      (            t            )                          =                                                            1                Cp                            ⁢                                                ∫                                      -                    ∞                                    t                                ⁢                                                      i                    ⁡                                          (                      τ                      )                                                        ⁢                                                                          ⁢                                      ⅆ                    τ                                                                        →                                          V                c                            ⁡                              (                s                )                                              =                                    1              sCp                        ⁢                                          i                ⁡                                  (                  s                  )                                            .                                                          [                  EQ          .                                          ⁢          1                ]            
When UP(t)=1, the top switch 206 closes and I1 will charge the equivalent loop filter capacitive load, C_LoopFilter. Therefore, Vc(t) will start increasing linearly with time. The opposite will happen if DOWN(t)=1. Assuming no offset or mismatch (an ideal case), PLL 100 using the charge pump in FIG. 2 will lock with zero steady-steady state phase error. A tiny phase error results in an indefinite charge accumulation on the loop filter 106 if phase lock is not sufficiently precise, resulting in phase jitter induced on the VCO 108, which is an undesirable condition. Having a precise phase lock point can reduce phase jitter. A precise phase lock point can be obtained from a precise (in time) resolution obtained from short delays and no dead time between UP and DOWN modes of operation.
Since prior art charge pumps, e.g., as shown in FIG. 2, are current-based devices, the effect of mismatch between I1 and I2 leads to reference spurs, which are undesirable. When the PLL is locked (e.g., CLOCK_Feedback matches CLOCK_Reference), both the reference and feedback signals are exactly the same in frequency and phase, which is the desired condition. Therefore, the switches in the CP will be on for only a short instant injecting currents I1 and −I2 to/from the loop filter 106. Ideally, I1=I2 in magnitude and the switches are perfect, leading to a net charge injected to/from CP being exactly zero.
Unfortunately, in practice, I1 and I2 are not 100% equal due to process variation, mismatch in the transistors and current mirrors, imperfect switches, and timing of the inputs. A significant problem with such current-based devices is that the net charge into/from the charge pump 102 is not zero, causing an error voltage ΔV across the loop filter 106. This causes the VCO frequency, which is controlled by the charge pump output, to shift corresponding to ΔV. This in turn causes the CLOCK_Feedback to not match the CLOCK_Reference signal. Since the PLL is a feedback loop system, the phase/frequency detector 104 and the charge pump 102 will have to constantly reset the voltage control line to the VCO to set its frequency and phase. Overall, the control voltage toggles between two values with the input frequency thus creating a sawtooth waveform which the loop filter 106 attempts to remove. The loop filter 106 generally has issues removing all of these variations. Any small unwanted movements on the control voltage signal will then produce tiny differences on the VCO frequency. This asymmetry of charge vs. discharge can be accommodated by the loop filter 106, but the modulation of control voltage also creates unwanted sidebands at the PLL output, which is an undesirable condition. These sideband (or spurs) can create a problem in both receivers and transmitters by causing noise.
Other common drawbacks or disadvantages of current-based PLL charge pumps include the following:
High power consumption (e.g., ˜0.5 mW to 1 mW with a supply voltage of 1.8 V in the prior art) due to the current mirrors (several currents going up and down to bias the charge pump). The currents must be run high enough to overcome the transients of switching the current mirrors on and off. Current mirrors are not easily switched on and off quickly and tend to take a long period of time to stabilize.
For prior art PLL charge pumps it can be difficult to switch current sources on and off for short periods of time, as is required for establishing a clean voltage for locked conditions. It takes time to turn linear current mirrors on and off, especially when their settling time to a constant current, and the residual burst of current at turn off are considered. The current mirrors in prior art PLL charge pumps are normally switched off by interrupting the source connection of the output current mirror. The current mirrors are switched on by connecting the current mirror source to its respective power rail (Vdd or Gnd). The gate-source voltage that controls the current mirror output is typically very small and thus sensitive to the current the current mirror produces. A drop in this at turn on and a spike at turn off produces transient errors in the output current. Since the gate-to-source voltage on the current mirrors controls their output current, it is not a good idea to have the switch in series with the gate-to-source connection of the mirror transistor (i.e., stacking the mirror on top of the switch).
One technique to mitigate the DC errors of the current mirror output for such current-based PLL charge pumps, has been to add an extra transistor, that is sized to match the necessary switch transistor, to the current mirror devices in a particular current mirror group. Those extra transistors that are added are typically all turned on hard (e.g., Vgs>>Vth). This can result in extra complexity and reduce robustness.
Another problem of prior art current-based PLL charge pumps can be that if there is any current flowing in the power supply wires that connect the current mirrors together, a voltage between the mirror transistors is established, which modulates the charge pump output current. Therefore, there are a lot of ways to pick up noise in current mirrors.
A further drawback of prior art current-based PLL charge pumps is that the mirror transistors are large and take up significant area on an integrated circuit. As feature sizes get smaller, current sources lose manufacturing repeatability (precision) thus matching current mirror transistors (which are typically large) becomes more difficult. As a result, current-based PLL charge pumps typically have employed designs with enough margin to dominate process parameter variations. Typically this has meant that the charge pumps have been designed to run at a higher current in order for all of the corner parameters to pass.
Additionally, such current-based charge pumps of the prior art typically have exhibited a large amount of noise near the equilibrium point (e.g., in phase lock); this can introduce noise on the control voltage output, which must be filtered in the loop filter to keep a stable VCO frequency and phase. Such noise is usually undesirable. For example, it is widely known that it is very important in radio frequency (RF) circuits to maintain a low jitter on the high frequency clock which is the VCO.